Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths

We address the problem of control synthesis for pipelined data paths. Two basic control schemes are possible: datastationary and time-stationary. In this work, we consider the latter approach. We developed an approach to automatically synthesize time-stationarycontrollers for pipelined data paths produced by high level synthesis tools. A highly optimized FSM controller is implemented using either PLAs or Standard Cells. We compared our approach to published work on FSM generation and optimization and the results indicate large savings in total controller area.